Output Signal of an Excitation Limiter

Within the framework of generic models, the signal(s) interfacing between an UEL/OEL/SCL and its respective exciter model is such that the output signal from an excitation limiter is either received at a summation point or a takeover gate at the exciter. These two types of location actually expect two different type of signals (differences are discussed later in this topic).

This means that a limiter model could be of a type that outputs a summation point signal or a takeover gate signal, or a limiter model's output could be configurable. Similarly, some exciters accept a limiter signal only at a summation point or only at a takeover gate, or they could also be configurable. Since a summation point limiter output signal is not compatible as an input signal at a takeover gate, and vice versa, this naturally brings up the question whether a specific limiter model is compatible with a specific exciter model. Also, there are certain older exciter models that do not have an input for an UEL/OEL/SCL – the exciter model would need to be upgraded to so that a limiter models can be used.

Inappropriate combination of an UEL/OEL/SCL and an exciter can cause exciters to have atypical signal clamping (if a summation point signal were to be fed into a takeover gate), or abnormally large error signals (if a takeover gate signal were to be fed into a summation point). Both this situations will result in weird and unintended consequences during the dynamic simulation. To understand why, it is important to draw the distinction between summation points and takeover gates.

• A summation point input signal at an exciter (from a compatible excitation limiter model) typically feeds in at the voltage reference signal. This serves to automatically modify the voltage reference signal in response to a control action from an UEL/OEL/SCL, and can occur in addition to manual changes to the voltage reference "knob" or digital reference.

  • When an UEL/OEL/SCL is not yet activated, the UEL/SCL_UEL/OEL/SCL_OEL signal should be zero.

  • When an UEL/SCL limiter is activated due to under-excitation, the UEL/SCL_UEL signal would be positive (typically between 0.1 to 0.3 p.u.).

  • When an OEL/SCL limiter is activated due to over-excitation, the OEL/SCL_OEL signal would be negative (typically between -0.3 to -0.1 p.u.).

  In general, a summation point output signal would typically vary around 0 ± 0.3 p.u.

• A takeover gate input signal at an exciter (from a compatible excitation limiter model) feeds in either at a high‑value select (HV) gate (for UEL/SCL_UEL signals) or at a low‑value select (LV) gate (for OEL/SCL_OEL signals). Respectively, this serves as a time-varying lower limit or upper limit to restrict the internal excitation signal, in response to a control action from an UEL/OEL/SCL.

  • When an UEL/OEL/SCL is not yet activated, the UEL/SCL_UEL (or OEL/SCL_OEL) signal should be less than the static lower limit (or greater than the static upper limit) at the exciter's internal.

  • When an UEL/SCL limiter is activated due to under-excitation, the UEL/SCL_UEL signal would be greater than the static lower limit at the exciter's internal.

  • When an OEL/SCL limiter is activated due to over-excitation, the OEL/SCL_OEL signal would be less than the static upper limit at the exciter's internal.

  In general, a takeover point output signal would typically not be around the value of 0 p.u.

PowerWorld Simulator has compatibility checks in place to prevent inappropriate UEL/OEL/SCL-exciter combinations. For example, excitation limiter OEL4C is not compatible with exciter ESST1A, because ESST1A only accepts a takeover gate OEL input signal but OEL4C can only provide a summation point OEL output signal.